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AMD’s EPYC 9005 “Turin” processors keep the SP5 socket of the previous “Genoa” generation but change almost everything inside it: new Zen 5 and dense Zen 5c cores, faster memory and a full-width AVX-512 datapath. For dedicated-server buyers, the practical question is less “how much faster” than “which kind of core”: a few fast ones, many dense ones, or a proven Genoa part that can still lead on throughput per dollar.
Genoa vs Turin at a glance
| Feature | EPYC 9004 “Genoa” | EPYC 9005 “Turin” |
|---|---|---|
| Core architecture | Zen 4 (Zen 4c in the 128-core 9754) | Zen 5 and Zen 5c |
| Maximum cores per socket | 96 (Zen 4), 128 (Zen 4c) | 128 (Zen 5), 192 (Zen 5c) |
| Cores sharing one 32 MB L3 | Up to 8 | Up to 8 (Zen 5), up to 16 (Zen 5c) |
| L1 data cache per core | 32 KB | 48 KB |
| AVX-512 execution | 256-bit datapaths, two cycles per 512-bit operation | Full 512-bit datapath |
| Memory | 12 channels, DDR5-4800 | 12 channels, DDR5-6000; DDR5-6400 where the platform enables it |
| Peak memory bandwidth per socket | 460.8 GB/s | 614 GB/s (at DDR5-6400) |
| PCIe lanes, single socket | 128 × PCIe 5.0 | 128 × PCIe 5.0 |
| CXL | 1.1+ | 2.0 |
| Highest TDP | 400 W (configurable) | 500 W |
| Socket | SP5 | SP5 |
Figures come from AMD’s datasheets and architecture white papers; cache sizes also appear in the system disclosures of published SPEC results. Two changes matter most in day-to-day use: the vector datapath and the memory subsystem.
Zen 5: wider vectors, higher IPC
AMD rates Zen 5 at up to 17% more instructions per clock than Zen 4 on enterprise and cloud workloads, and up to 37% more on AI and HPC workloads. Those are geomeans from AMD’s internal fixed-frequency testing, so treat them as a direction rather than a forecast for your application.
The largest single change is AVX-512. Zen 4 supports the instruction set but, in AMD’s words, executes two 256-bit vectors in sequential clock cycles for each 512-bit operation. Zen 5 has a full 512-bit datapath and adds the VP2INTERSECT instruction. Software already vectorized for AVX-512 gains the most: compression, cryptography, media encoding, scientific code and CPU inference. Code that is not vectorized sees the IPC gain alone.
To check whether your stack benefits, look for avx512f in the CPU flags reported by lscpu, then in your software’s release notes. Many libraries select AVX-512 code paths at run time; self-compiled code needs a matching target, for example -march=native when you build on the server itself.
Zen 5c and the 192-core EPYC 9965
Zen 5c is the same architecture and instruction set in a denser layout. A Zen 5 compute die carries up to 8 cores sharing 32 MB of L3; a Zen 5c die carries 16 cores sharing the same 32 MB. The EPYC 9965 combines 12 of them for 192 cores and 384 MB of L3, or 2 MB per core. The 32-core 9355P sits at the other extreme: eight dies with four active cores each, so every group of four cores shares a full 32 MB.
The trade is per-core speed for density. The 9965 has a 2.25 GHz base clock and boosts to 3.7 GHz, and published SPEC CPU 2017 results put its per-core integer throughput at a little over half that of the 9355P. For container platforms, web tiers and batch jobs that scale across cores, that is a good trade. For software licensed per core, or anything bound by the latency of a few threads, it is not.
Memory and I/O: 12 channels, faster DIMMs
Both generations have 12 DDR5 channels per socket. Genoa supports DDR5-4800, which AMD rates at 460.8 GB/s of peak bandwidth per socket. Turin supports DDR5-6000, and AMD’s current datasheet lists DDR5-6400 with one DIMM per channel where the server manufacturer enables it, for up to 614 GB/s. Maximum capacity stays at 6 TB per socket with two DIMMs per channel.
Peak bandwidth assumes every channel is populated with identical modules. If your workload is bandwidth-bound, such as in-memory analytics, simulation or large caches, ask any provider how many DIMMs a configuration uses: a 12-channel CPU with 8 DIMMs cannot reach its rated bandwidth.
The lane count does not change: 128 PCIe 5.0 lanes in a single-socket server, and up to 160 in two-socket Turin systems. CXL moves from 1.1+ to 2.0, which matters mainly to platforms that add CXL memory expanders.
Same socket, not always the same server
Turin uses SP5, the socket introduced with Genoa, and AMD describes it as compatible with the broadly deployed SP5 platform. The fine print matters: AMD tells buyers to check with the server manufacturer whether a given 9004-era system supports 9005 CPUs. Firmware is one reason; power is another. Genoa-generation parts top out at a 400 W configurable TDP, while the largest Turin parts, including the 9965, are rated at 500 W.
For a dedicated-server customer, this is mostly the provider’s concern. It is still worth knowing when comparing “Turin” offers: the CPU model alone does not describe the platform around it.
The PowerDedi EPYC line-up compared
Our EPYC range spans one Genoa part and three Turin parts. Clock speeds and TDP are AMD’s specifications; memory, storage and prices are our standard configurations.
| CPU | Generation | Cores / threads | Base / all-core / max boost | L3 | TDP | RAM, storage | Price per month |
|---|---|---|---|---|---|---|---|
| EPYC 9454P | Zen 4 “Genoa” | 48 / 96 | 2.75 / 3.65 / 3.8 GHz | 256 MB | 290 W | 256 GB DDR5 ECC, 2 × 3.84 TB NVMe | $489 |
| EPYC 9355P | Zen 5 “Turin” | 32 / 64 | 3.55 / 4.2 / 4.4 GHz | 256 MB | 280 W | 384 GB DDR5 ECC, 2 × 3.84 TB NVMe Gen5 | $519 |
| EPYC 9555P | Zen 5 “Turin” | 64 / 128 | 3.2 / 4.2 / 4.4 GHz | 256 MB | 360 W | 768 GB DDR5 ECC, 4 × 3.84 TB NVMe Gen5 | $949 |
| EPYC 9965 | Zen 5c “Turin Dense” | 192 / 384 | 2.25 / 3.35 / 3.7 GHz | 384 MB | 500 W | 1.5 TB DDR5 ECC, 4 × 7.68 TB NVMe Gen5 | $1,790 |
| CPU | SPECrate 2017 integer base, one socket (published range) | Per core, median | L3 per core | RAM per core | Price per core |
|---|---|---|---|---|---|
| EPYC 9454P | 510–540 (median 521) | 10.9 | 5.3 MB | 5.3 GB | $10.19 |
| EPYC 9355P | 440–490 (median 470) | 14.7 | 8 MB | 12 GB | $16.22 |
| EPYC 9555P | 728–864 (median ≈ 812) | 12.7 | 4 MB | 12 GB | $14.83 |
| EPYC 9965 | 1,260–1,630 (median 1,525) | 7.9 | 2 MB | 8 GB | $9.32 |
The SPEC column is the range of single-socket results published on spec.org as of September 2026, excluding virtual-machine submissions: 16 results for the 9454P, 19 for the 9355P, 14 for the 9555P and 12 for the 9965. They come from vendor-tuned systems, mostly with all 12 memory channels populated, so they show relative throughput between CPUs, not the performance of any particular server, ours included.
Read together, the two tables show the trade-offs plainly. Per dollar of monthly price, the Genoa 9454P delivers the most integer throughput: about 1.07 SPEC points per dollar, against 0.85–0.91 for the three Turin parts. Per core, the 9355P is about 35% faster than the 9454P, which is what the extra $30 a month buys. The 9965 packs more than three times the 9355P’s throughput into one server, at the lowest price per core.
Who should pick which
- EPYC 9454P, $489 a month. The most integer throughput per dollar in this line-up, on a mature platform, delivered in about 15 minutes. A good fit for virtualization hosts, CI runners, build farms and general multi-tenant work. Its 2.75 GHz base clock and double-pumped AVX-512 make it the weaker choice for latency-sensitive or vector-heavy code.
- EPYC 9355P, $519 a month. The fastest cores in the range: 3.55 GHz base, 4.2 GHz all-core boost, 8 MB of L3 and 12 GB of RAM per core. Pick it for databases, game and trading back ends, blockchain validators and software licensed per core. It trails the 9454P on total throughput.
- EPYC 9555P, $949 a month. Sixty-four fast cores with 768 GB of RAM and four Gen5 NVMe drives. It suits large VM hosts, in-memory data sets, analytics and RPC-style services that need cores and memory together.
- EPYC 9965, $1,790 a month. The most throughput per server and the lowest price per core, with 1.5 TB of RAM and about 30 TB of Gen5 NVMe. Built for scale-out: containers, web tiers, batch processing and high VM density. Avoid it for per-core licensing or single-thread latency.
Rule of thumb: choose by the constraint you actually hit. A few hot threads: 9355P. Many parallel jobs on a budget: 9454P. Cores and memory together: 9555P. Maximum density: 9965.
All four run with ECC memory, NVMe storage and a 10 Gbps unmetered port; delivery ranges from about 15 minutes for the 9454P to 72 hours for the 9965. Current stock and locations are on the AMD EPYC page.
Sources
- AMD Launches 5th Gen AMD EPYC CPUs — AMD, 10 October 2024
- AMD EPYC 9005 Series Server CPUs datasheet — AMD, November 2025
- AMD EPYC 9005 Processor Architecture Overview — AMD white paper, April 2025
- 4th Gen AMD EPYC Processor Architecture — AMD white paper
- AMD EPYC 9454P specifications — AMD
- AMD EPYC 9355P specifications — AMD
- AMD EPYC 9555P specifications — AMD
- AMD EPYC 9965 specifications — AMD
- SPEC CPU 2017 integer rate results — Standard Performance Evaluation Corporation
